`timescale 1ns / 1ps

module ps_top(
    // spi
    output  o_fpga_spi0_mosi          ,
    output  o_fpga_spi0_sclk          ,
    output  o_hmc7044_spi_slen        ,
    inout   io_hmc7044_spi_sdata      ,
    output  o_hmc7044_spi_sclk        ,
    output  o_lmx2594_a_spi1_ss       ,
    input   i_lmx2594_a_spi1_miso     ,
    output  o_lmx2594_a_spi1_mosi     ,
    output  o_lmx2594_a_spi1_sclk     ,                           
    output  o_lmx2594_b_spi1_ss       ,
    input   i_lmx2594_b_spi1_miso     ,
    output  o_lmx2594_b_spi1_mosi     ,
    output  o_lmx2594_b_spi1_sclk     ,                           
    output  o_lmx2594_c_spi1_ss       ,
    input   i_lmx2594_c_spi1_miso     ,
    output  o_lmx2594_c_spi1_mosi     ,
    output  o_lmx2594_c_spi1_sclk     ,   
    
    // gpio emio define
    output  o_rfdc_rst              ,
    inout   o_i2c_reset_b           ,
    inout   i_int_adt7516           ,
    inout   i_hmc7044_gpio3         ,
    inout   i_hmc7044_gpio2         ,
    inout   i_hmc7044_gpio1         ,
    inout   o_hmc7044_rst           ,
    inout   o_hmc7044_sync          ,
    // gpio configure IP address
    inout   i_id1                   ,
    inout   i_id2                   ,
    inout   i_id3                   ,
    inout   i_id4                   ,
    // external fpga load
    inout   i_zynq2vu_done          ,
    inout   i_vu_init_b             ,
    inout   o_vu_prog_b             ,
    
    // axi2apb
    output [31 : 0]     o_axi_apb_araddr,
    output [2 : 0]      o_axi_apb_arprot,
    input               i_axi_apb_arready,
    output              o_axi_apb_arvalid,
    output [31 : 0]     o_axi_apb_awaddr,
    output [2 : 0]      o_axi_apb_awprot,
    input               i_axi_apb_awready,
    output              o_axi_apb_awvalid,
    output              o_axi_apb_bready,
    input [1 : 0]       i_axi_apb_bresp,
    input               i_axi_apb_bvalid,
    input [31 : 0]      i_axi_apb_rdata,
    output              o_axi_apb_rready,
    input [1 : 0]       i_axi_apb_rresp,
    input               i_axi_apb_rvalid,
    output [31 : 0]     o_axi_apb_wdata,
    input               i_axi_apb_wready,
    output [3 : 0]      o_axi_apb_wstrb,
    output              o_axi_apb_wvalid,
    output              o_axi_lite_clk,
    
    // rf_dc
    input adc0_clk_clk_n,
    input adc0_clk_clk_p,
    input adc1_clk_clk_n,
    input adc1_clk_clk_p,
    input adc2_clk_clk_n,
    input adc2_clk_clk_p,
    input adc3_clk_clk_n,
    input adc3_clk_clk_p,
    input dac0_clk_clk_n,
    input dac0_clk_clk_p,
    input dac1_clk_clk_n,
    input dac1_clk_clk_p,
   
    input sysref_in_diff_n, 
    input sysref_in_diff_p,
    
    input user_sysref_adc_0,
    input user_sysref_dac_0,
    
    input vin0_01_v_n,
    input vin0_01_v_p,
    input vin0_23_v_n,
    input vin0_23_v_p,
    input vin1_01_v_n,
    input vin1_01_v_p,
    input vin1_23_v_n,
    input vin1_23_v_p,
    input vin2_01_v_n,
    input vin2_01_v_p,
    input vin2_23_v_n,
    input vin2_23_v_p,
    input vin3_01_v_n,
    input vin3_01_v_p,
    input vin3_23_v_n,
    input vin3_23_v_p,
    output vout00_v_n,
    output vout00_v_p,
    output vout01_v_n,
    output vout01_v_p,
    output vout02_v_n,
    output vout02_v_p,
    output vout03_v_n,
    output vout03_v_p,
    output vout10_v_n,
    output vout10_v_p,
    output vout11_v_n,
    output vout11_v_p,
    output vout12_v_n,
    output vout12_v_p,
    output vout13_v_n,
    output vout13_v_p,
     
    output [127 : 0]    m00_axis_0_tdata,
    input               m00_axis_0_tready,
    output              m00_axis_0_tvalid,
    output [127 : 0]    m02_axis_0_tdata,
    input               m02_axis_0_tready,
    output              m02_axis_0_tvalid,
    input               m0_axis_aclk_0,
    input               m0_axis_aresetn_0,
    output [127 : 0]    m10_axis_0_tdata,
    input               m10_axis_0_tready,
    output              m10_axis_0_tvalid,
    output [127 : 0]    m12_axis_0_tdata,
    input               m12_axis_0_tready,
    output              m12_axis_0_tvalid,
    input               m1_axis_aclk_0,
    input               m1_axis_aresetn_0,
    output [127 : 0]    m20_axis_0_tdata,
    input               m20_axis_0_tready,
    output              m20_axis_0_tvalid,
    output [127 : 0]    m22_axis_0_tdata,
    input               m22_axis_0_tready,
    output              m22_axis_0_tvalid,
    input               m2_axis_aclk_0,
    input               m2_axis_aresetn_0,
    output [127 : 0]    m30_axis_0_tdata,
    input               m30_axis_0_tready,
    output              m30_axis_0_tvalid,
    output [127 : 0]    m32_axis_0_tdata,
    input               m32_axis_0_tready,
    output              m32_axis_0_tvalid,
    input               m3_axis_aclk_0,
    input               m3_axis_aresetn_0,
    output              o_pl_resetn0,
    input [255 : 0]     s00_axis_0_tdata,
    output              s00_axis_0_tready,
    input               s00_axis_0_tvalid,
    input [255 : 0]     s01_axis_0_tdata,
    output              s01_axis_0_tready,
    input               s01_axis_0_tvalid,
    input [255 : 0]     s02_axis_0_tdata,
    output              s02_axis_0_tready,
    input               s02_axis_0_tvalid,
    input [255 : 0]     s03_axis_0_tdata,
    output              s03_axis_0_tready,
    input               s03_axis_0_tvalid,
    input               s0_axis_aclk_0,
    input               s0_axis_aresetn_0,
    input [255 : 0]     s10_axis_0_tdata,
    output              s10_axis_0_tready,
    input               s10_axis_0_tvalid,
    input [255 : 0]     s11_axis_0_tdata,
    output              s11_axis_0_tready,
    input               s11_axis_0_tvalid,
    input [255 : 0]     s12_axis_0_tdata,
    output              s12_axis_0_tready,
    input               s12_axis_0_tvalid,
    input [255 : 0]     s13_axis_0_tdata,
    output              s13_axis_0_tready,
    input               s13_axis_0_tvalid,
    input               s1_axis_aclk_0,
    input               s1_axis_aresetn_0
       
    );

 wire [15:0]  zynq_gpio_i   ;
 wire [13:0]  zynq_gpio_o   ; // [gpio15,gpio14] [gpio11:gpio0]
 wire [15:0]  zynq_gpio_t   ;
 wire [13:0]  ps_emio       ; // inout 
 wire emio_rst              ; // gpio429  -- gpio_13
 wire tmp_gpio12            ; // gpio428  -- gpio_12
 assign ps_emio = {
    o_i2c_reset_b         , // gpio431  ---  gpio_15
    i_int_adt7516         , // gpio430  ---  gpio_14
    i_hmc7044_gpio3       , // gpio427  ---  phase  -- gpio_11
    i_hmc7044_gpio2       , // gpio426  ---  pll2
    i_hmc7044_gpio1       , // gpio425  ---  pll1 
    o_hmc7044_rst         , // gpio424
    o_hmc7044_sync        , // gpio423
    i_id4                 , // gpio422
    i_id3                 , // gpio421
    i_id2                 , // gpio420
    i_id1                 , // gpio419
    i_zynq2vu_done        , // gpio418
    i_vu_init_b           , // gpio417
    o_vu_prog_b             // gpio416  338 + 78 = 416
 };
 assign o_rfdc_rst = emio_rst;
 
 wire spi0_miso;
 wire spi0_mosi;
 wire spi0_sclk;
 wire spi0_ss0;
 wire spi0_ss1;
 wire spi0_ss2;
 wire spi1_miso;
 wire spi1_mosi;
 wire spi1_sclk;
 wire spi1_ss0;
 wire spi1_ss1;
 wire spi1_ss2;
 
 wire axi_lite_clk;
 
 BUFG  u_clk_glbl_bufg  (.O (o_axi_lite_clk), .I (axi_lite_clk));
 ps_spi ps_spi_inst (    
    .o_spi0_miso     (spi0_miso),
    .i_spi0_mosi     (spi0_mosi),
    .i_spi0_sclk     (spi0_sclk),
    .i_spi0_ss0      (spi0_ss0),
    .i_spi0_ss1      (spi0_ss1),
    .i_spi0_ss2      (spi0_ss2),

    .o_spi1_miso     (spi1_miso),
    .i_spi1_mosi     (spi1_mosi),
    .i_spi1_sclk     (spi1_sclk),
    .i_spi1_ss0      (spi1_ss0),
    .i_spi1_ss1      (spi1_ss1),
    .i_spi1_ss2      (spi1_ss2),
    // external fpga spi load                  
    .o_fpga_spi0_mosi          (o_fpga_spi0_mosi),
    .o_fpga_spi0_sclk          (o_fpga_spi0_sclk),
    //HMC7044
    .o_hmc7044_spi0_ss         (o_hmc7044_spi_slen),
    .io_hmc7044_sdata          (io_hmc7044_spi_sdata),
    .o_hmc7044_spi0_sclk       (o_hmc7044_spi_sclk),
    //lmx2594_a                           
    .o_lmx2594_a_spi1_ss       (o_lmx2594_a_spi1_ss),
    .i_lmx2594_a_spi1_miso     (i_lmx2594_a_spi1_miso),
    .o_lmx2594_a_spi1_mosi     (o_lmx2594_a_spi1_mosi),
    .o_lmx2594_a_spi1_sclk     (o_lmx2594_a_spi1_sclk),
    //lmx2594_b                           
    .o_lmx2594_b_spi1_ss       (o_lmx2594_b_spi1_ss),
    .i_lmx2594_b_spi1_miso     (i_lmx2594_b_spi1_miso),
    .o_lmx2594_b_spi1_mosi     (o_lmx2594_b_spi1_mosi),
    .o_lmx2594_b_spi1_sclk     (o_lmx2594_b_spi1_sclk),
    //lmx2594_c                           
    .o_lmx2594_c_spi1_ss       (o_lmx2594_c_spi1_ss),
    .i_lmx2594_c_spi1_miso     (i_lmx2594_c_spi1_miso),
    .o_lmx2594_c_spi1_mosi     (o_lmx2594_c_spi1_mosi),
    .o_lmx2594_c_spi1_sclk     (o_lmx2594_c_spi1_sclk)
            
    );

 gpio_conv u_gpio_conv (
   .o_zynq_gpio  ( zynq_gpio_i ),
   .i_zynq_gpio  ( zynq_gpio_o ),
   .i_zynq_gpio_t( zynq_gpio_t ),
   .io_dev_gpio  ( ps_emio     )
 );

 design_soc_wrapper u_design_soc_wrapper (
   // [15:0]
    .emio_gpio_i_0      (zynq_gpio_i),
    .emio_gpio_o_0      ({zynq_gpio_o[13:12], emio_rst, tmp_gpio12, zynq_gpio_o[11:0]}),
    .emio_gpio_t_0      (zynq_gpio_t),

    .spi0_miso          (spi0_miso),
    .spi0_mosi          (spi0_mosi),
    .spi0_sclk          (spi0_sclk),
    .spi0_ss0           (spi0_ss0),
    .spi0_ss1           (spi0_ss1),
    .spi0_ss2           (spi0_ss2),
    .spi1_miso          (spi1_miso),
    .spi1_mosi          (spi1_mosi),
    .spi1_sclk          (spi1_sclk),
    .spi1_ss0           (spi1_ss0),
    .spi1_ss1           (spi1_ss1),
    .spi1_ss2           (spi1_ss2),

    .axi_apb_araddr     (o_axi_apb_araddr),
    .axi_apb_arprot     (o_axi_apb_arprot),
    .axi_apb_arready    (i_axi_apb_arready),
    .axi_apb_arvalid    (o_axi_apb_arvalid),
    .axi_apb_awaddr     (o_axi_apb_awaddr),
    .axi_apb_awprot     (o_axi_apb_awprot),
    .axi_apb_awready    (i_axi_apb_awready),
    .axi_apb_awvalid    (o_axi_apb_awvalid),
    .axi_apb_bready     (o_axi_apb_bready),
    .axi_apb_bresp      (i_axi_apb_bresp),
    .axi_apb_bvalid     (i_axi_apb_bvalid),
    .axi_apb_rdata      (i_axi_apb_rdata),
    .axi_apb_rready     (o_axi_apb_rready),
    .axi_apb_rresp      (i_axi_apb_rresp),
    .axi_apb_rvalid     (i_axi_apb_rvalid),
    .axi_apb_wdata      (o_axi_apb_wdata),
    .axi_apb_wready     (i_axi_apb_wready),
    .axi_apb_wstrb      (o_axi_apb_wstrb),
    .axi_apb_wvalid     (o_axi_apb_wvalid),
    .axi_lite_clk       (axi_lite_clk),
    .pl_resetn0         (o_pl_resetn0),
    
    .adc0_clk_clk_n(adc0_clk_clk_n),
    .adc0_clk_clk_p(adc0_clk_clk_p),
    .adc1_clk_clk_n(adc1_clk_clk_n),
    .adc1_clk_clk_p(adc1_clk_clk_p),
    .adc2_clk_clk_n(adc2_clk_clk_n),
    .adc2_clk_clk_p(adc2_clk_clk_p),
    .adc3_clk_clk_n(adc3_clk_clk_n),
    .adc3_clk_clk_p(adc3_clk_clk_p),
    .dac0_clk_clk_n(dac0_clk_clk_n),
    .dac0_clk_clk_p(dac0_clk_clk_p),
    .dac1_clk_clk_n(dac1_clk_clk_n),
    .dac1_clk_clk_p(dac1_clk_clk_p),
        
    .m00_axis_0_tdata(m00_axis_0_tdata),
    .m00_axis_0_tready(m00_axis_0_tready),
    .m00_axis_0_tvalid(m00_axis_0_tvalid),
    .m02_axis_0_tdata(m02_axis_0_tdata),
    .m02_axis_0_tready(m02_axis_0_tready),
    .m02_axis_0_tvalid(m02_axis_0_tvalid),
    .m0_axis_aclk_0(m0_axis_aclk_0),
    .m0_axis_aresetn_0(m0_axis_aresetn_0),
    
    .m10_axis_0_tdata(m10_axis_0_tdata),
    .m10_axis_0_tready(m10_axis_0_tready),
    .m10_axis_0_tvalid(m10_axis_0_tvalid),
    .m12_axis_0_tdata(m12_axis_0_tdata),
    .m12_axis_0_tready(m12_axis_0_tready),
    .m12_axis_0_tvalid(m12_axis_0_tvalid),
    .m1_axis_aclk_0(m1_axis_aclk_0),
    .m1_axis_aresetn_0(m1_axis_aresetn_0),
    
    .m20_axis_0_tdata(m20_axis_0_tdata),
    .m20_axis_0_tready(m20_axis_0_tready),
    .m20_axis_0_tvalid(m20_axis_0_tvalid),
    .m22_axis_0_tdata(m22_axis_0_tdata),
    .m22_axis_0_tready(m22_axis_0_tready),
    .m22_axis_0_tvalid(m22_axis_0_tvalid),
    .m2_axis_aclk_0(m2_axis_aclk_0),  // #
    .m2_axis_aresetn_0(m2_axis_aresetn_0),
    
    .m30_axis_0_tdata(m30_axis_0_tdata),
    .m30_axis_0_tready(m30_axis_0_tready),
    .m30_axis_0_tvalid(m30_axis_0_tvalid),
    .m32_axis_0_tdata(m32_axis_0_tdata),
    .m32_axis_0_tready(m32_axis_0_tready),
    .m32_axis_0_tvalid(m32_axis_0_tvalid),
    .m3_axis_aclk_0(m3_axis_aclk_0), // #
    .m3_axis_aresetn_0(m3_axis_aresetn_0),  
    
    .s00_axis_0_tdata(s00_axis_0_tdata),
    .s00_axis_0_tready(s00_axis_0_tready),
    .s00_axis_0_tvalid(s00_axis_0_tvalid),
    .s01_axis_0_tdata(s01_axis_0_tdata),
    .s01_axis_0_tready(s01_axis_0_tready),
    .s01_axis_0_tvalid(s01_axis_0_tvalid),
    .s02_axis_0_tdata(s02_axis_0_tdata),
    .s02_axis_0_tready(s02_axis_0_tready),
    .s02_axis_0_tvalid(s02_axis_0_tvalid),
    .s03_axis_0_tdata(s03_axis_0_tdata),
    .s03_axis_0_tready(s03_axis_0_tready),
    .s03_axis_0_tvalid(s03_axis_0_tvalid),
    .s0_axis_aclk_0(s0_axis_aclk_0), // #
    .s0_axis_aresetn_0(s0_axis_aresetn_0),
    
    .s10_axis_0_tdata(s10_axis_0_tdata),
    .s10_axis_0_tready(s10_axis_0_tready),
    .s10_axis_0_tvalid(s10_axis_0_tvalid),
    .s11_axis_0_tdata(s11_axis_0_tdata),
    .s11_axis_0_tready(s11_axis_0_tready),
    .s11_axis_0_tvalid(s11_axis_0_tvalid),
    .s12_axis_0_tdata(s12_axis_0_tdata),
    .s12_axis_0_tready(s12_axis_0_tready),
    .s12_axis_0_tvalid(s12_axis_0_tvalid), 
    .s13_axis_0_tdata(s13_axis_0_tdata),
    .s13_axis_0_tready(s13_axis_0_tready),
    .s13_axis_0_tvalid(s13_axis_0_tvalid),
    .s1_axis_aclk_0(s1_axis_aclk_0), // #
    .s1_axis_aresetn_0(s1_axis_aresetn_0),  
      
    .sysref_in_diff_n(sysref_in_diff_n),
    .sysref_in_diff_p(sysref_in_diff_p),
    
    .user_sysref_adc_0(user_sysref_adc_0),
    .user_sysref_dac_0(user_sysref_dac_0),
    
    .vin0_01_v_n(vin0_01_v_n),
    .vin0_01_v_p(vin0_01_v_p),
    .vin0_23_v_n(vin0_23_v_n),
    .vin0_23_v_p(vin0_23_v_p),
    .vin1_01_v_n(vin1_01_v_n),
    .vin1_01_v_p(vin1_01_v_p),
    .vin1_23_v_n(vin1_23_v_n),
    .vin1_23_v_p(vin1_23_v_p),
    .vin2_01_v_n(vin2_01_v_n),
    .vin2_01_v_p(vin2_01_v_p),
    .vin2_23_v_n(vin2_23_v_n),
    .vin2_23_v_p(vin2_23_v_p),
    .vin3_01_v_n(vin3_01_v_n),
    .vin3_01_v_p(vin3_01_v_p),
    .vin3_23_v_n(vin3_23_v_n),
    .vin3_23_v_p(vin3_23_v_p),
    .vout00_v_n(vout00_v_n),
    .vout00_v_p(vout00_v_p),
    .vout01_v_n(vout01_v_n),
    .vout01_v_p(vout01_v_p),
    .vout02_v_n(vout02_v_n),
    .vout02_v_p(vout02_v_p),
    .vout03_v_n(vout03_v_n),
    .vout03_v_p(vout03_v_p),
    .vout10_v_n(vout10_v_n),
    .vout10_v_p(vout10_v_p),
    .vout11_v_n(vout11_v_n),
    .vout11_v_p(vout11_v_p),
    .vout12_v_n(vout12_v_n),
    .vout12_v_p(vout12_v_p),
    .vout13_v_n(vout13_v_n),
    .vout13_v_p(vout13_v_p)
 );

 
endmodule
